The present invention pertains to microprocessor memory systems and more particularly to a circuit for refreshing dynamic RAM memory on a shared basis.
In memory storage systems of computer systems, dynamic RAM memory is a useful and economical storage medium. One drawback to the use of such RAM memory devices is that the memory must be periodically refreshed in order to maintain the integrity of the data stored within it. To accomplish this end, central processing unit (CPU) access to the memory must be interrupted in order to provide this refreshing function to the RAM memory.
Typical solutions to the refresh problem are as follows. Computer access of the memory is interrupted and a large block of the memory is refreshed. This solution has a shortcoming in that CPU access of the memory during the time of refresh is completely blocked. In an on-line real time system, such memory access blockage of the CPU is intolerable. To overcome this problem, some systems will operate the refreshing circuitry with a clock signal of a very high rate in order to minimize the time during which CPU access of the memory is blocked. While this situation is more tolerable than the previous solution discussed above, the CPU is still delayed in responding to external stimuli during the period of the refresh cycle. In large process control systems such as telephone processing systems, such delay would result in lost telephone calls.
It is the object of the present invention to provide an efficient and economical RAM memory refresh circuit which operates on a shared basis with the CPU in order to be real time efficient.
It is another object of the invention to provide a RAM refresh circuit which will provide interlock control for other external devices to interrupt the CPU's processing.